| MAKETA Project Status | |||
| Project File: | Maketa.ise | Current State: | Programming File Generated |
| Module Name: | Boot |
|
No Errors |
| Target Device: | xc2s200e-6pq208 |
|
106 Warnings |
| Product Version: | ISE 9.2.01i |
|
Fri Dec 21 22:49:36 2007 |
| MAKETA Partition Summary | |||
| No partition information was found. |
| Device Utilization Summary | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops | 622 | 4,704 | 13% | |
| Number of 4 input LUTs | 2,916 | 4,704 | 61% | |
| Logic Distribution | ||||
| Number of occupied Slices | 1,983 | 2,352 | 84% | |
| Number of Slices containing only related logic | 1,983 | 1,983 | 100% | |
| Number of Slices containing unrelated logic | 0 | 1,983 | 0% | |
| Total Number of 4 input LUTs | 3,568 | 4,704 | 75% | |
| Number used as logic | 2,916 | |||
| Number used as a route-thru | 140 | |||
| Number used for Dual Port RAMs | 512 | |||
| Number of bonded IOBs | 30 | 142 | 21% | |
| IOB Flip Flops | 1 | |||
| Number of Block RAMs | 13 | 14 | 92% | |
| Number of GCLKs | 1 | 4 | 25% | |
| Number of GCLKIOBs | 1 | 4 | 25% | |
| Total equivalent gate count for design | 271,136 | |||
| Additional JTAG gate count for IOBs | 1,488 | |||
| Performance Summary | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
| Timing Constraints: | All Constraints Met | ||
| Detailed Reports | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | Current | Thu Dec 20 20:13:52 2007 | 0 | 89 Warnings | 14 Infos |
| Translation Report | Current | Fri Dec 21 19:41:54 2007 | 0 | 0 | 0 |
| Map Report | Current | Fri Dec 21 19:42:23 2007 | 0 | 16 Warnings | 2 Infos |
| Place and Route Report | Current | Fri Dec 21 19:45:26 2007 | 0 | 1 Warning | 3 Infos |
| Static Timing Report | Current | Fri Dec 21 19:45:43 2007 | 0 | 0 | 3 Infos |
| Bitgen Report | Current | Fri Dec 21 19:46:05 2007 | 0 | 0 | 0 |